Semiconductor memory devices typically access stored data in multiple bit quantities. For example, in response to an applied address, output data could be provided in one or more groups of eight-bit bytes (often referred to as words). By accessing data in this manner, rapid amounts of data can be read or written in a single memory cycle. To further increase the rate at which data can be accessed, many semiconductor memories have "pipelined" architectures. In response to an applied control signal, typically a clock, sequences of bits are rapidly shifted out of the device through a series of stages. Commonly, pipelined architectures are used in synchronous random access memories (RAM), in which data bits are shifted in response to an externally applied system clock. Synchronous RAMs can come in both dynamic and static forms.
While synchronous devices can provide a faster overall data throughput, such devices will have a given latency between access operations and command inputs. For example, while an address may be applied for a read operation on a first clock cycle, the resulting output data may not be available for two or three clock cycles.
While most memory device applications use all the bits provided by a memory device in a given read or write operation, it can be desirable to read or write to only selected bits within a number of accessed bits. For example, while a memory device may provide 16-bits in parallel in a given read operation, it may be desirable to read only the upper or lower byte of data. Furthermore, when reading and writing graphics data, it may be desirable to access only certain predetermined bits within a byte. For such applications, the use of read and write "masks" are employed.
In the case of a read mask, when a number of bits are read from the memory device, selected outputs will provide data, while masked outputs, will not provide data, but instead will be placed in a predetermined state. The predetermined state could be a "tri-state" (a high impedance state) or a given logic level (high or low). In the case of a write mask, when a number of bits are applied to data inputs, selected inputs will allow their respective data to be written into the memory, while masked inputs will not allow their respective data to be written into the memory device.
For pipelined architectures, masked read and write operations must be properly timed with the data being pipelined into, or out of, the memory device. As in the case of an applied address, the application of a mask command may have some latency, particularly in the case of a read mask operation. A problem in synchronous RAMs having mask command latency may arise due to a "race" condition between the mask command path, and the data read path. The mask command propagates along the mask command path to arrive at an output driver, and disable the output driver. At the same time, a data bit (that is to be masked) is propagating along the data read path to the same output driver. In the event the mask command arrives too late, the output driver may be activated for a short time in response to the data bit, rather than be disabled completely. This can produce erroneous output disturbance during that time.
An example of an undesirable race condition is illustrated in FIGS. 1 and 2. FIG. 1 is a block diagram illustrating a portion of a single data bit output path, and a masked read command path. FIG. 2 is a timing diagram illustrating the operation of the block diagram of FIG. 1 that gives rise to an erroneous output data "bump."
Referring now to FIG. 1, a read mask circuit is designated by the general reference character 100. The read data mask circuit is shown to include a mask command path 102 having a first mask latch 104, that is controlled by a clock signal (CLK), arranged in series with a second mask latch 106, also controlled by the clock signal. The output of the second mask latch 106, shown as MASK(n), is provided as an "output enable" input to an output driver 108. In the event the OE.sub.13 input is low, the output driver 108 will provide an output signal according to a data input signal, received at a DIN input. In the event the OE.sub.13 signal is high, the output driver 108 will be disabled, and provide a tri-state output. The read mask circuit 100 further includes a portion of a data bit pipeline 110, having a first data latch 112 in series with a second data latch 114. The first and second data latches (112 and 114) are both controlled by the clock signal. It is additionally understood that while FIG. 1 shows MASK(n) directly connected to the OE.sub.13 input of the output driver, in most designs the OE.sub.13 is generated by a plurality of signals that are logical-ORd together with MASK(n) being one of the signals.
The operation of the read mask circuit 100 is best understood with reference to FIG. 1 in conjunction with FIG. 2. FIG. 2 includes a number of waveforms illustrating various signals shown in FIG. 1. The CLK signal is the internal clock signal. The MASK signal illustrates the input to the first mask latch 104. A high MASK signal indicates a mask command propagating through the mask command path 102. The MASK signal in FIG. 2 has a latency of two. That is, once a high MASK signal appears at the input of the first mask latch 104, the output bit appearing at the output driver 108 two clock cycles later, will be masked. The output of the first mask latch 104 is shown as MASK(n-1), the output of the second mask latch 106, is shown as MASK(n). (MASK(n) is also the OE.sub.13 input to the output driver 108).
The data at various points in the data pipeline are also illustrated in FIG. 2. The input to the first data latch 112 is shown as DATA(n-2). The output of the first data latch 112 is shown as DATA(n-1). The output of the second data latch 114 is shown as DATA(n). DATA(n) is also the DIN input to the output driver 108. Finally, the output of the output driver 108 is shown as DQ.
The waveforms of FIG. 2 illustrate the pipelined read of six data bits, shown as B0-B5. The fourth bit, B3 is to be masked. Further, it is assumed that the logic of bit B3 is different from that of bit B2. Various time periods are illustrated in FIG. 2, beginning with time t0.
At time t0, the CLK signal is low. No MASK command has been applied, and so the MASK, MASK(n-1) and MASK(n) waveforms are low. Three data bits are in the data pipeline 110 at this time. Bit B0 is stored in the second data latch 114, resulting in the DATA(n) signal being the value of B0. Bit B1 is stored in the first data latch 112, resulting in the DATA(n-1) signal being the value of B1. Finally, bit B2 is present at the input of the first data latch 112, resulting in the DATA(n-2) signal being the value of B2. Because the MASK(n) signal is low, the OE.sub.13 input is low, and the output driver 108 is enabled, providing a DQ output equivalent to the DIN input (bit B0).
At time t1, the CLK signal transitions to a high level. During the same clock style, the MASK waveform goes high, indicating the reading in of a mask-command at the input of the chip, and hence at the input to the first data latch 104. For the purposes of this description it is assumed that there is some propagation delay within the mask command path 102, more so than in the data bit pipeline 110. Accordingly, the MASK signal transitions high a certain delay after time t1. Because the high MASK transition has not yet propagated through the mask command path 102, the MASK(n) and MASK(n-1) waveforms are low.
In response to the high CLK signal at time t1, data propagates through the data pipeline 110. As a result, the DATA(n), DATA(n-1) and DATA(n-2) waveforms illustrate the shifted data, storing the B1, B2 and a B3 bit, respectively. Because the MASK(n) (OE.sub.13 input) remains low, the DQ output changes to the B1 value.
At time t2, the CLK signal transitions to a high level once again. No new mask command has been entered, and so the MASK waveform returns low shortly after time t2. At the same time, the MASK signal goes low, the second mask latch 106 shifts the mask command one more step along the mask command path 102. Consequently, the MASK(n-1) waveform goes high. The MASK(n) signal remains low.
Also at time t2, the data bits in the pipeline propagate to the next stage in the pipeline. A new data bit, B4 is present at the input to the first data latch 112. Bit B3 (the bit to be masked) is latched in the first data latch 112, resulting the DATA(n-1) signal being equal to B3. The B2 data bit is latched in the second data latch 114. Because the OE.sub.13 input remains low, the DQ waveform is equal to the B2 bit value.
At time t3, the CLK signal begins a third cycle, and transitions high a third time. Because the mask command path 102 is delayed with respect to the data bit pipeline 110, the MASK(n-1) and MASK(n) waveforms remain high and low, respectively, at time t2. In contrast, the data bit pipeline 110 continues to shift data bits in synchronism with the CLK signal. In other words, in the race condition between the data pipeline 110 and the mask command path 102, the data pipeline 110 wins. As a result, at time t3, the second data latch 114 latches the bit B3 prior to the OE.sub.13 input going high, and so the DQ output transitions to the B3 value at time t3. This creates an undesirable erroneous data "bump" at the data output.
At time t4, the MASK(n-1)signal goes low, and the MASK(n) signal transitions high. The output driver 108 is disabled, and the DQ output is placed in a tri-state condition. The data bump is terminated, but only after it has caused an erroneous transition in the DQ output.
It would be desirable to provide a read mask circuit that does not suffer from the adverse effects of the race condition illustrated above.